反向恢复特性.docxVIP

Examination of reverse recovenr lossesin a synchronous buck converter circuit Introduction A synchronous buck convener is a commonly used topology fbr step down DC lo DC conversion applications. A schematic of this topology is shown in Fig. 1. The step down ratio Kui/Vm is controlled by changing the duty cycle of the control FET (QI). To improve efficiency it is desirable lo have the sync FET (Q2) turned on when QI is turned off However, due to finite FET turn-on and turn-off time the state of two FETs cannot be switched instantaneously. Figure 1. PN body diode in parallel with the FETs. To maintain current flow through inductor L after the control FET switches off, the bottom diode will conduct until lhe sync FET turns on. A state diagram depicting the possible switching modes of a sync buck converter is shown in Fig. 2. Under normal operation of the sync buck circuit, the switching sequence is B-A-C-A-B. The dwell time in state A is commonly referred to as dead time. To improve cfYicicncy the designers would like to reduce the dead time to a minimal duration. However, if the dead time is reduced below the turn-on or tum-off time of the FETs, the switches may go to state D, instead of state A. State D is often referred to as shoot-through when both transistors arc on at the same time shorting the input supply. This state should be avoided as it can result in significant loss of efficiency and could damage the FETs. The switches drive an inductive load as shown in Fig. I. When the circuit transitions from state B to A, the current through the inductor cannot instantly drop to zero and will continue to flow through the PN body diode of sync FET Q2. The diode will conduct the cunent through the inductor until the bottom FET can be turned on in state C. Generally, during state A, current flows through the diode. In this paper, we would like to discuss the impact of conduction through the diode on the efficiency of the sync buck converter. D Figure 2. State diagram sho