2021 数字逻辑设计 期末考试-试题及参考解答 1.docxVIP

2021 数字逻辑设计 期末考试-试题及参考解答 1 2021lbrack;数字逻辑设计rsqb;期末考试-试题及参考解答lpar;1rpar; ………密………封………线………以………内………答………题………无………效…… 电子科技大学2021 -2021学年第 二 学期期 末 考试 A 卷 课程名称：_数字逻辑设计及应用__ 考试形式： 闭卷 考试日期： 20 14 年 07 月 10 日 考试时长：_120___分钟 课程成绩构成：平时 30 %， 期中 30 %， 实验 0 %， 期末 40 % 本试卷试题由___六__部分构成，共__8___页。 1. A circuit with 10 flip-flops can store ( 10 ) bit binary numbers, that is, include ( 1024 或 210 ) states at most. 2. A 5-bit linear feedback shift-register (LFSR) counter with no self-correction can have ( 31 或 25-1 ) normal states. 3. A modulo-24 counter circuit needs ( 5 ) D filp-flops at least. A modulo-500 counter circuit needs ( 3 ) 4-bit counters of 74x163 at least. 4. If an 74x148 priority encoder has its 1, 3, 4, and 5 inputs at the active level, the active LOW binary output is ( 010 ) . 5. State/output table for a sequential circuit is shown as Table 1. X is input and Z n is output. Assume that the initial state is S 0, if the input sequence is X = the output sequence should be (或110011000 ). 【可以确定的输出序列应该有9位】 n+1n 21 6. Transition/output table for a sequential circuit is shown in Table 2, X is input and Y is output, the sequential circuit is a modulus ( 3 ) up/down counter. ………密………封………线………以………内………答………题………无………效…… 7. A serial sequence generator by feedback shift registers 74x194 is shown in Figure 1, assume the initial state is Q 2Q 1Q 0 = 100, the feedback function LIN = Q2’Q1’ + Q2Q 0’, the output sequence in Q2 is ( 100110 循环输出 ). Figure 1 8. When the input isof an 8 bit DAC, the corresponding output voltage is 3.76V. The output voltage 28?1255 range for the DAC is ( 0 ~ 9.99 或 3. 76×6 或 )V. 【本题并未对误差范围进行要求，3. 76×5 一般可保留2位小数。由于考试时没有计算器，写出算式也可】 1. The output signal of ( A ) circuit is 1-out-of-M code. A. binary decoder B. binary encoder C. seven-segment decoder D. decade counter 2. An asynchronous counter differs from a synchronous in ( B ). A. the number of