第二章硬件描述语言vhdl2016.pptxVIP

第二章;2.1 引言;2.2 VHDL的基础知识;8位计数器的功能描述: ARCHITECTURE behav_count OF counter IS  SIGNAL counter_data: INTEGER RANGE 0 TO 255; BEGIN PROCESS( clk,clear,load ) BEGIN IF ( clear =‘0’ ) THEN counter_data=0; ELSIF ( clk ‘EVENT AND clk=‘1’ ) THEN IF ( load=‘1’ ) THEN counter_data =data_in; ELSE  IF ( ena=‘1’) THEN IF counter_data=255 THEN counter_data=0; ELSE counter_data=counter_data+1; ENDIF