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- 约2.55千字
- 约 2页
- 2022-04-15 发布于福建
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library ieee;
use ieee.std_logic_1164.all;
entity anjianzibian is
port(res:in std_logic;
clk,din:in std_logic;
dout:out std_logic);
end entity;
architecture hev of anjianzibian is
type states is(s0,s1,s2,s3);
signal state,next_s:states;
begin
process(clk,res,state)
begin
if res=1 then
state=s0;
elsif clkevent and clk=1 then
state=next_s;
case state is
when s0=
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