分析adi tigersharc培训ts201处理器l11.pptxVIP

I/O Processor 2 TigerSHARC DSP M0 M2 M10 Sequencer 128b J ALU 128b 128b K ALU 128b Comp block X ALU Mult Shift I/O Processor DMA Controller 2 Computation blocks X and Y Comp block Y ALU Mult Shift 128b Register file Register file Link Ports External Bus … 3 I/O Processor Functions I/O Processor is responsible for all external communication: host processor/controller external RAM/ROM other TigerSHARC processors All communication takes place over the 64-bit external bus the 4 link ports (4-bit) Communication transactions via the external port or link ports can be transactions controlled by the core processor DMA transactions Transactions over the external port can also be controlled by other bus masters 4 Single Processor Configuration - External Bus External Port: 32-bit address 64-bit data 125 Mhz 1000 Mbytes/sec Host Processor SRAM SDRAM Tiger SHARC External bus Memory Mapped Devices External Port 5 Multiproc. Cluster Configuration - Parallel Ports Max 8 TigerSHARCs External bus Host Processor SRAM SDRAM Memory Mapped Devices Tiger SHARC Tiger SHARC Tiger SHARC Tiger SHARC 6 Host I/O SRAM SDRAM Tiger SHARC Tiger SHARC Tiger SHARC Tiger SHARC Bus connections Link Port connections MP Cluster Configuration Link Ports 7 I/O Processor - 1 -Introduction The I/O Processor is connected to core processor and internal memory via the four internal 128-bit buses I/O processor manages all off-chip communication including: bus requests buffering between internal and external buses bus arbitration packing and unpacking between 128-bit wide internal data and 8/32/64-bit external data DMA and direct transfers SDRAM transfers Internal buses External Port Link Port DMA Controller Core Processor Internal Memory External Bus I/O Processor 8 TigerSHARC DMA Controller DMA Controller INTERNAL BUS Data Address Control 128-bit DATA 32-bit ADDR I/O Processor DMAR IFIFO OFIFO OBUF Bus Interface Unit Link Interface Unit LP0 I/O Buffers LP1 I/O Buffers LP2 I/O Buffers LP3 I/O Buff