EDA实训资料1·全加器全减器程序.docxVIP

给出 1 位全减器的 VHDL 描述。首先设计 1 位半减器，然后用例化语句将它们连接起来 xin x diff d x diff diffout yin y s_out y s_out sub_in f e sub_out 底层文件半减器（h_suber）程序设计： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY h_suber IS PORT ( x , y : IN STD_LOGIC; diff , s_out : OUT STD_LOGIC ) ; END ENTITY h_suber; ARCHITECTURE fh1 OF h_suber IS SIGNAL abc : STD_LOGIC_VECTOR ( 1 DOWNTO 0 ) ; BEGIN abc = x y ; PROCESS ( abc ) BEGIN CASE abc IS WHEN 00 = diff = 0; s_out = 0 ; WHEN 01 = diff = 1; s_out = 1 ; WHEN 10 = diff = 1; s_out = 0 ; WHEN 11 = diff = 0; s_out = 0 ; WHEN OTHER = NULL ; END CASE; END PROCESS; END ARCHITECTURE fh1 ; 底层文件或门（or2a）程序设计： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY or2a IS PORT ( a , b : IN STD_LOGIC; c : OUT STD_LOGIC ) ; END ENTITY or2a; ARCHITECTURE one OF or2a IS BEGIN C = a OR b ; END ARCHITECTURE one; 根据连接图，顶层文件全减器（f_suber）程序设计： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY f_suber IS PORT ( xin , yin , sub_in : IN STD_LOGIC; diffout , sub_out : OUT STD_LOGIC ) ; END ENTITY f_suber; ARCHITECTURE fd1 OF f_suber IS COMPONENT h_suber PORT ( x , y : IN STD_LOGIC; diff , s_out : OUT STD_LOGIC ) ; END COMPONENT ; COMPONENT or2a PORT ( a , b : IN STD_LOGIC; c : OUT STD_LOGIC ) ; END COMPONENT ; SIGNAL d , e , f : STD_LOGIC; BEGIN u1 : h_suber PORT MAP ( x = xin , y = yin , diff = d , s_out = e ); u2 : h_suber PORT MAP ( x = d , y = sub_in , diff = diffout , s_out = f ); u3 : or2a PORT MAP ( a = f , b = e , c = sub_out ); END ARCHITECTURE fd1; 全加器程序参照自动化同学课本，原理与全减器类似。