IBMPCAT硬件架构与动作原理.pptVIP

POST (Power-On Self Test) Process POST tests and initializes the following : The central processing unit ( CPU ) The ROM BIOS ( checksum ) The CMOS RAM The Intel 8237 DMA Controller The keyboard controller The base 64K System RAM The Programmable Interrupt controller * 8. The Programmable Interrupt Timer 9. The cache controller 10. COMS RAM configuration data 11.The CRT controller 12. RAM memory above 64K 13. The keyboard 14. Diskette drive A availability 15. The serial interface circuitry 16. The diskette controller 17. The fixed disk controller 18. Any additional hardware * AWARD BIOS POST Test code listing POST CODE Award POST Routine Description C0 Turn off chipset cache. 01 Test processor flag register. 02 Test all processor registers except SS,SP and BP with pattern FF and 00. 03 Initialize Chips(RTC,8254,8237,8259),Reset math coprocessor,Clear CMOS shutdown byte and page register. 04 Test DRAM refresh 05 Blank video,keyboard controller initialization. 07 Test CMOS interface and battery status. BE Initialize chipset with power on BIOS defaults. C1 Memory-presence test.(OEM Specific-Test to size on-board memory) * C5 C6 Early Shadow.(OEM Specific-Early Shadow enable for fast boot) Cache presence test. ( External cache size detection) 08 Setup low memory(base 64K memory test). 09 Early cache initialization (Cyrix CPU initialization,Cache Initialization.) 0A Setup interrupt vector table. 0B Test CMOS RAM checksum,load default value if test is bad. 0C Initialize keyboard(detect keyboard type and set NUM_LOCK status) 0D Initialize and detect video adapter interface. 0E Test video memory,write sign-on message to screen.Setup shadow RAM-Enable shadow according to setup. 0F Test DMA controller 0. 10 Test DMA controller 1. * 11 Test DMA page registers(74612) 14 Test Timer 0 counter 2 15 Test 8259-1 interrupt mask register(port 21H) 16 Test 8259-2 interrupt mask register(port A1H) 17 Test stuck 8259’s interrupt bits 18 Test 8259 interrupt functionality * IB