英特尔® MAX® 10 通用 I-O 用户指南.pdf

® ® Intel MAX 10 General Purpose I/O User Guide ® ® Updated for Intel Quartus Prime Design Suite: 22.1 Online Version ID: 683751 Send Feedback UG-M10GPIO Version: 2022.10.31 Contents Contents ® ® 1. Intel MAX 10 I/O Overview3 1.1. Intel MAX 10 Devices I/O Resources Per Package 4 1.2. Intel MAX 10 I/O Vertical Migration Support 5 2. Intel MAX 10 I/O Architecture and Features6 2.1. Intel MAX 10 I/O Standards Support 6 2.1.1. Intel MAX 10 I/O Standards Voltage and Pin Support9 2.2. Intel MAX 10 I/O Elements12 2.2.1. Intel MAX 10 I/O Banks Architecture13 2.2.2. Intel MAX 10 I/O Banks Performance14 2.2.3. Intel MAX 10 I/O Banks Locations 14 2.3. Intel MAX 10 I/O Buffers18 2.3.1. Schmitt-Trigger Input Buffer18 2.3.2. Programmable I/O Buffer Features 18 2.4. I/O Standards Termination 26 2.4.1. Voltage-Referenced I/O Standards Termination 26 2.4.2. Differential I/O Standards Termination27 2.4.3. Intel MAX 10 On-Chip I/O Termination 28 3. Intel MAX 10 I/O Design Considerations 31 3.1. Guidelines: VCCIO Range Considerations 31 3.2. Guidelines: Voltage-Referenced I/O Standards Restriction 32 3.3. Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers32 3.4. Guidelines: Adhere to the LVDS I/O Restrictions Rules 33 3.5. Guidelines: I/O Restriction Rules33 3.6. Guidelines: Placement Restrictions for 1.0 V I/O Pin 34 3.6.1. Calculating the Total Inductance for 1.0 V Pin Placement 34