尺寸格式信息spm sc9832a v single 6l.pptx

SizeformatandSizeinformationPCBSupportGroup.1

SPM_SP9832A_V1.1.0_EMCP_0201_TOP_Double_6L_29.75*28.65SPRDPCBModulePlatformNameVersionExternalMemoryPCBDecalBBchipPositionTOPAllComponentsPlacementPCBLayersMeasure(mm)

.3SpreadtrumConfidentialMeasure

PISISimulationReportHW_PCB_Support.4SpreadtrumConfidential

Contents .5BasicInformationPI(PowerIntegrity)Simulation(1)SimulationSetup (2)PIResult3.SI(SignalIntegrity)Simulation(1)SimulationSetup(2)SICrossTalkResult4.Summary

PlatformProjectNameReportdateSC9832A+LPDDR3SPM_SC9832A_V1.0.1_0201_TOP_Single_6L_29.75X28.652015.10.101.BasicInformation.6ReferenceStack-upSpreadtrumConfidential

参考仿真Stack-Up，对于6层一阶PCB走线：L1-L2之间的介质厚度最好不要超过75um；L2-L3之间的介质厚度一定不能超过125um；L3-L4之间的介质厚度可以根据情况适当的调整；一般叠层结构近似为对称，因此L4-L6参考L1-L3的意见；Stack-UpSuggestion.7SpreadtrumConfidential

电源走线尽量短且宽；各电源的去耦电容靠近BB摆放，接地端通过孔与主地连接；VDDARM最好是用平面形式连接电源和去耦电容；VDDARM宽度不小于2mm，VDDCORE和VDDMEM宽度不小于1.5mm。电源相临层必须有完整的参考地，上下两层均有完整的地平面为最好。2.PISuggestion.8SpreadtrumConfidential

PISimulationModel .9Setup: ShortedatpointA,simulatetheeffectiveinductanceandDCR. Theinputimpedancemustlowerthantargetimpedance. Thetargetimpedanceisourexperiencevalue.SpreadtrumConfidential

PIResult(1)_VDDARM.10DCR(mohm)EffectiveInductance(nH)Target150.72Result5.80.46SummarypassSpreadtrumConfidential

PIResult(2)_VDDCORE.11DCR(mohm)EffectiveInductance(nH)Target150.64Result7.50.57SummarypassSpreadtrumConfidential

PIResult(3)_BBVDDMEM.12DCR(mohm)EffectiveInductance(nH)Target200.4Result30.33SummarypassSpreadtrumConfidential

PIResult(4)_MEMVDDMEM.13DCR(mohm)EffectiveInductance(nH)Target200.48Result2.50.12SummarypassSpreadtrumConfidential

差分线必须紧邻走线，两根差分走线的走线间距保持一倍线宽；Address走线与差分Clock走线长度差控制在+/-3mm以内；Address走线尽量做到单根包地处理，如果不能但跟包地的话要保证相邻走线间距在3倍线宽以上；Data走线尽量走在L2层，减少对表层GND的破坏；3.SISugge