verilogHDL交通灯设计21完整版.doc

交通灯设计

第一模块分频模块

把50MHz分成1Hz

moduledivider(clk_50MHz,clk_1Hz);

inputclk_50MHz;

outputclk_1Hz;

regclk_1Hz;

reg[30:0]count;

parameterN=

always@(posedgeclk_50MHz)

begin

if(count==N/2-1)

begin

clk_1Hz=clk_1Hz+1b1;

count=0;

end

else

count=count+1b1;

end

endmodule

第二模块60进制计数器程序：

modulecounter60(clkin,reset,countnum);

inputclkin,reset;//reset复位

output[5:0]countnum;

reg[5:0]countnum;

always@(posedgeclkin)

begin

if(!reset)

countnum=0;

else

begin

if(countnum==59)//六十进制计数

countnum=0;

else

countnum=countnum+1;

end

end

endmodule

第三模块控制器

程序：

modulecontrol(clk,countin,start_sn,start_ew,redn,reds,rede,redw,greenn,greens,greene,greenw);

inputclk;

input[5:0]countin;//60进制计数器

outputstart_sn,start_ew; //控制东西、南北方向倒计时控制开关

outputredn,reds,rede,redw; //东西南北红灯开关

outputgreenn,greens,greene,greenw; //东西南北绿灯开关

regstart_sn,start_ew;

regredn,reds,rede,redw;

reggreenn,greens,greene,greenw;

always@(posedgeclk)

begin

if(countin==0)

begin

start_sn=1;

start_ew=0;

end

elseif(countin=1countin=24)

begin

start_sn=0;

start_ew=0;

greenn=0;

greens=0;

greene=1;

greenw=1;

redn=1;

reds=1;

rede=0;

redw=0;

end

elseif(countin24countin30)

begin

start_sn=0;

start_ew=0;

greenn=0;

greens=0;

greene=0;

greenw=0;

redn=1;

reds