多周期控制器实现代码.pdfVIP

--Company:

--Engineer:

--

--CreateDate:09:53:3304/13/2012

--DesignName:GaoXueCheng

--ModuleName:Controler_seven-Behavioral

--ProjectName:Controler_seven

--TargetDevices:

--Toolversions:

--Description:

--

--Dependencies:

--

--Revision:

--Revision0.01-FileCreated

--AdditionalComments:

--

libraryIEEE;

useIEEE.STD_LOGIC_1164.ALL;

--Uncommentthefollowinglibrarydeclarationifusing

--arithmeticfunctionswithSignedorUnsignedvalues

--useIEEE.NUMERIC_STD.ALL;

--Uncommentthefollowinglibrarydeclarationifinstantiating

--anyXilinxprimitivesinthiscode.

--libraryUNISIM;

--useUNISIM.VComponents.all;

entityControler_sevenis

Port(rst:inSTD_LOGIC;

clk:inSTD_LOGIC;

clk0:inSTD_LOGIC;

instructions:inSTD_LOGIC_VECTOR(15downto0);

light:outSTD_LOGIC_VECTOR(15downto0);

showCtrl:instd_logic;

bZero_ctrl:instd_logic);

endControler_seven;

architectureBehavioralofControler_sevenis

signalbzero:std_logic;

typeshower_stateis(PC,ALU,Mem,Reg);

signalshower:shower_state;

typecontroler_stateis(instruction_fetch,decode,execute,mem_control,write_reg);

signalstate:controler_state;

signalPCWrite:std_logic;

signalPCWriteCond:std_logic;

signalPCSource:std_logic;

signalALUOp:std_logic_vector(1downto0);

signalALUSrcA:std_logic;

signalALUSrcB:std_logic_vector(1downto0);

signalMemRead:std_logic;

signalMemWrite:std_logic;

signalIRWrite:std_logic;

signalMemtoReg:std_logic_vector(1downto0);

signalRegWrite:std_logic_vector(2downto0);

signalRegDst:std_logic_vector(1downto0);

signalIorD:std_logic;

signaltmpb_zero:std_logic;

signaltmp_light:std_logic_vector(15downto0);

begin

light=tmp_light;

process(c