成果综合xapp chronous fifo desgin同步FIFODESGIN.pdfVIP

APPLICATIONNOTE

SynchronousandAsynchronous

FIFODesigns

XAPP051September17,1996(Version2.0)ApplicationNotebyPeterAlfke

Summary

ThisapplicationnotedescribesRAM-basedFIFOdesignsusingthedual-portRAMinXC4000-Seriesdevices.

Synchronousdesignswithacommonread/writeclockaredescribed,aswellasasynchronousdesignswitht

readandwriteclocks.Emphasisisonthefast,efficientandreliablegenerationofthehandshakesignalsFULLandEMPTY,

whichdeterminedesignperformance.

XilinxFamilyDemonstrates

XC4000E,XC4000L,XC4000EX,XC4000XLFIFOdesigntechniques

Introduction

Table1:FIFODesignPerformance,XC4000E-3Device

ManyXC4000-SeriesdesignsusethedistributedRAMfea-

turetoimplementFirst-In-First-Out(FIFO)elasticbufferstoNo.ofSimultaneousReadandWrite

formabridgweensubsystemswithdifferentclockCLBsSynch.SpeedAsynch.Speed

ratesandaccessrequirements.16x16FIFO2365MHz50MHz

Thenon-synchronousnatureofthesingle-portRAMin32x8FIFO2850MHz40MHz

XC4000confrontsthedesignerwithseveralchallenges.64x8FIFO4850MHz40MHz

Addressesmustbemultiplexed,treadand

writeclocksmustbesynchronized,andaccessrequests