基于vhdl时钟设计说明书.docVIP

12/24小时数字钟设计顶层图

12/24小时数字钟设计顶层图

二、模块和程序

1、计数器25000

libraryieee;

useieee.std_logic_1164.all;

useieee.std_logic_unsigned.all;

entityyourname_cnt25000is

port(clk:instd_logic;

clkout:outstd_logic);

endyourname_cnt25000;

architecturebavofyourname_cnt25000is

signalcnt:integerrange0to24999;

begin

process(clk)

begin

ifclkeventandclk=1then

ifcnt=24999then

cnt=0;

else

cnt=cnt+1;

endif;

ifcnt12500then

clkout=1;

else

clkout=0;

endif;

endif;

endprocess;

endbav;

2、去抖模块

libraryieee;

useieee.std_logic_1164.all;

useieee.std_logic_unsigned.all;

entityyourname_qudouis

port(key_in,clk_1kHz:instd_logic;

key_out:outstd_logic);

endyourname_qudou;

architecturebehavofyourname_qudouis

signalcnt20:integerrange0to19;

begin

process(clk_1kHz,key_in)

begin

ifclk_1kHzeventandclk_1kHz=1then

ifcnt20=19then

cnt20=0;

key_out=key_in;

else

cnt20=cnt20+1;

endif;

endif;

endprocess;

endbehav;

3、万年历模块

万年历顶层电路图

①年月日星期模块

libraryieee;

useieee.std_logic_1164.all;

useieee.std_logic_unsigned.all;

entityyourname_ymdxis

port(

preset:instd_logic;

co:instd_logic;

date:outstd_logic_vector(7downto0);

month,year:outstd_logic_vector(7downto0);

xingqi:outstd_logic_vector(3downto0));

endyourname_ymdx;

architecturebavofyourname_ymdxis

signalyue:std_logic_vector(7downto0):

signalnian:std_logic_vector(7downto0):

signalri:std_logic_vector(7downto0):

signalxingqi1:std_logic_vector(3downto0):=0010;

signalcnt:std_logic_vector(7downto0):

signalqm:integerrange28to31;

begin

process(yue,nian)

begin

caseyueis

whenqm=31;

when

if(nian(0)=0)and(nian(1)=0)thenqm=29;

elseqm=28;endif;

wheqm=31;

when0