伯克利-芯片串行中的时钟到数据通道纠偏 Clock to Data Lane Deskew in Chiplet SerDes.pdfVIP

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伯克利-芯片串行中的时钟到数据通道纠偏 Clock to Data Lane Deskew in Chiplet SerDes.pdf

ClocktoDataLaneDeskewinChipletSerDes

JessicaFan

ElectricalEngineeringandComputerSciences

UniversityofCalifornia,Berkeley

TechnicalReportNo.UCB/EECS-2026-192

/Pubs/TechRpts/2026/EECS-2026-192.html

May15,2026

Copyright©2026,bytheauthor(s).

Allrightsreserved.

Permissiontomakedigitalorhardcopiesofallorpartofthisworkfor

personalorclassroomuseisgrantedwithoutfeeprovidedthat

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