数字设计--第七章.ppt

Chapter7 Sequential Logic Design Principles (时序逻辑设计原理 ) Types of Logic Circuits Combinational logic circuit Outputs depend only on the current values of the inputs No feedback loop, No Memory Device Sequential logic circuit Outputs depend on - the current values of the inputs - the past values of the inputs Feedback loop, Memory Device Sequential Logic Circuit Sequential Logic Circuit – Output depends on current and previous inputs – Hold/store previous information (i.e., state) – The state is a collection of state variables. – A circuit with n binary state variables has 2n possible states. – So sequential circuits are sometimes called Finite State Machine (FSM) We need a clock The state changes of most sequential circuits occcur at times specified by a free-running clock signal. Chapter Outline Latches and Flip-Flops (锁存器和触发器 ) Clocked Synchronous State-Machine Analysis (同步时序分析) Clocked Synchronous State-Machine Design (同步时序设计) 7.1 Bistable Elements (双稳态元件) Metastable Behavior(亚稳态特性) Metastability is the situation where the inputs cause an indeterminate output in a feedback circuit Random Noise will tend to Drive a circuit that is Operating at the Metastable Point to one of the Stable operating point. ( 随机噪声会驱动工作于亚稳态点的电路转移到一个稳态的工作点上去 ) Metastable Behavior(亚稳态特性) 7.2 Latches and Flip-Flops(锁存器与触发器) The Basic Building Blocks of most Sequential Circuits. Latches（锁存器） A sequential device watches its inputs continuously and can change its outputs at any time In some cases requiring an enable signal to be asserted. Flip-Flops（ F/F,触发器） A sequential device samples its inputs and changes its outputs only when a clocking signal is changing. Latches and Flip-Flops S-R Latch S-R Latch with Enable D Latch Edge-Triggered D Flip-Flops Edge-Triggered D Flip-Flops with Enable Scan Flip-Flops Master/Slave Flip-Flops (S-R、J-K） Edge-Triggered J-K Flip-Flops T Flip-Flop S-R Latches S-R Latches S-R Latches S-R Latches S-R Latches S’-R’ latch S-R Latch