A Low-Power Capacitive Charge Pump Based Pipelined ADC资料.pdfVIP

1016 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 5, MAY 2010 A Low-Power Capacitive Charge Pump Based Pipelined ADC Imran Ahmed, Member, IEEE, Jan Mulder, and David A. Johns, Fellow, IEEE Abstract—A low-power pipelined ADC topology is presented In the interest of prolonging battery life in mobile systems, which uses capacitive charge pumps, source-followers, and dig- recently there has been a shift to achieve even more power ital calibration to eliminate the need for power-hungry opamps savings afforded from opamp-based techniques by substituting to achieve good linearity in a pipelined ADC. The differential charge pump technique achieves 10-bit linearity, and does not the opamp with alternative, more power efficient circuitry. For require an explicit common-mode-feedback circuit. The ADC was example, in [9] opamps with capacitive-feedback are replaced designed to operate at 50 MS/s in a 1.8 V, 0.18 m CMOS process, with open-loop resistively loaded differential-pairs, where where measured results show the peak SNDR and SFDR of the a digital DSP calibrates the gain nonlinearity introduced by ADC to be 58.2 dB (9.4 ENOB), and 66 dB respectively. The ADC using an open-loop approach. Low-power is achieved as the consumes 3.9 mW for all active circuitry and 6 mW for all clocking and digital circuits. open-loop gain stages do not require a large DC-gain, thus sim- plifying the MDAC circuit. Fur