第七讲信号和变量.pptVIP

7.1 常量 7.2 信号 实现代码：---错误使用信号的例子 LIBRARY ieee； USE ieee.std_logic_1164.all; entity count_ones is port ( din: IN std_logic_vector(7 downto 0); ones: OUT integer range 0 to 8); end count_ones; architecture not_ok of count_ones is signal temp: integer range 0 to 8; begin process (din) begin temp=0; FOR i IN 0 TO 7 LOOP IF (din(i) =‘1’) then temp=temp+1; END if; END LOOP; ones=temp; end process; end not_ok; 7.3 变量(variable) 例：“1”计数器的实现代码： LIBRARY ieee； USE ieee.std_logic_1164.all; entity count_ones is port ( din: IN std_logic_vector(7 downto 0); ones: OUT integer range 0 to 8); end count_ones; architecture ok of count_ones is variable temp: integer range 0 to 8; begin process (din) begin temp：=0; FOR i IN 0 TO 7 LOOP IF (din(i) =‘1’) then temp：=temp+1; END if; END LOOP; ones=temp; end process; end ok; 7.4 信号和变量的比较 （补充） 例7.3：多路复用器的对比设计 方案一：使用信号（not OK） LIBRARY ieee； USE ieee.std_logic_1164.all; entity mux is port ( a, b, c, d, s0, s1: IN std_logic; y: OUT std_logic); end mux; architecture not_ok of mux is signal sel: integer range 0 to 3; begin process (a, b, c, d, s0, s1) begin sel=0; if (s0=‘1’) then sel=sel+1; end if; if (s1=‘1’) then sel=sel+2; end if; case sel is when 0=y=a; when 1=y=b; when 2=y=c; when 3=y=d; end case; end process; end not_ok; 例7.3： 方案二：使用变量