基于FPGA全流水线的高质量图像旋转.docVIP

  FPGA-based fully pipelined and high-quality image rotation  5 10 15 20 25 30 35  Abstract: This paper focuses on the low latency and the fully pipelined implementation of image rotation with memory reduction on FPGA’s board. The method we used is based on three-pass algorithm and cubic convolution interpolation. The difficulty of the work is the construction of the fully pipeline as it is hard to get the positional relationship of pixels without storing them after shearing. In this article, mechanisms on judging the row offset and column offset is presented to select pixels in the same row or same column for interpolation in template, which solves the bottleneck of pipeline. Finally, the results of rotation, summary of the memory consumption in FPGA, and the comparison with existing method are presented. Key words: :Image rotation; three-pass algorithm; cubic convolution interpolation; FPGA pipelined implementation 0 Introduction Digital image rotation is widely used in the fields of military, aerospace and medical imaging. As we know, traditional image rotation is performed in 2-D space. Since the coordinates of pixels after shearing are not integers, we must use 2-D interpolation, and an n-degree (n≥3) interpolation is needed for higher quality. All of this above makes it complicated and time-consuming. So implementation of rotation by software will take too much time to calculate and can’t be up to real-time. As implemented on hardware, the trade-off between quality of the image and complexity of the approach should be considered. The author[1] implemented image rotation in DSP, and test some methods of interpolation, but the throughput is only 25 frames per second for video images, large number of memory is needed, and the calculation speed limits the process of high-quality request. So for higher speed, there is need to introduce FPGA. As implemented on FPGA’s board, the author is inclined to use external memory to store the temporary results for pixels’