数字逻辑--可调节电子表课程报告.docVIP

可调节电子表 摘 要 在设计过程中，首先对总体进行了分析论证，选择最佳设计方案。然后进行了系统功能模块的电路分析，主要是通过Quartus II仿真软件对电路进行了仿真和分析，在整个设计过程中，采用模块化设计方法，软件部分用硬件描述语言VHDL进行编程，以Quartus II为设计开发平台。本系统有两大部分组成：校时电路和显示电路。校时电路的设计是用74160和一些逻辑器件完成对电子表的功能，用三个开关控制校时和复位，并设置秒脉冲和手动脉冲，分别在上升沿时起作用。效果是只对分钟和小时校正；当校时时，秒脉冲无效；当正常计数时，手动秒冲无效；当手动脉冲有上升沿时，相应的位加1，其它位照常计数，不受校时手动脉冲影响；当按下复位按钮时，显示全部为零，重新计时。显示电路使用用VHDL编写LCD液晶显示器的显示程序。当校时电路和显示电路设计成功后，分别封装，然后组合在一起完成整个电子表的顶层电路图，下载验证设计是否正确。 关键词：可调节，电子表，Quartus II，VHDL,LCD液晶显示，硬件设计 Adjustable electronic ABSTRACT This design is a kind of adjustable electronic. In the design process, first on overall analyzed, choose the best design. Then, system function module circuit analysis, mainly through the circuit Quartus II simulation software are simulated and analyzed, in the whole design process, modular design method, the software partly in hardware description language programming, to Quartus VHDL development platform. For the design of the II This system has two main components: reset circuit and display circuit. Reset circuit design is to use 74160 and some logical device for electronic function, complete with three switch control reset and reset, and set the second pulse and manual pulse, when respectively in the rising edge played a role. Effect of minutes and hours just calibration; When school always, second pulse invalid; When normal count, manual seconds blunt invalid; When manual pulse is rising, the corresponding along a add 1, other bits as usual when, not affected by school counts influence; the manual pulse When press the reset button, display all for zero, to the timer. Show circuit with VHDL use written LCD display program. When reset circuit and display circuit design, respectively, after success together, then encapsulated top finish the whole electronic circuit diagram, download validation design is correct. KEY WORDS: Adjustable ，， ，VHDL，Circuit 前　言 1 第1章 课程设计目的、要求及任务 2 1.1 设计目的 2 1.2 设计任务及要求 2 第2章 课程设计环境 3 2.1 Quartus II介绍 3 2.2 VHDL语言 3 第3章可调电子表设计原理 5 3.1 设计原件选择及说明 5 3.2 各模块电路设计及原