基于VerilogHDL的DDR2SDRAM控制器设计周亮.pdf

第33 卷第8 期 合肥工业大学学报( 自然 科 学 版 ) Vol. 33 No. 8 2010 年8月 JOURNAL OF H EFEI UNIVERSITY OF TECH NOLOGY Aug. 2010 Doi: 10. 3969/j. issn. 1003 5060. 2010. 08. 031 Verilog HDL DDR2 SDRAM 周 亮, 王 娟, 胡畅华, 杨明武, 高挺挺 ( , 230009) :DDR2 SDRAM , , ( TOP DOWN) , Verilog , Modelsim 61 1 , Synopsys DC , Altera FPGA , DDR2 SDRAM : DDR2 SDRAM; ;Verilog H DL; FPGA :T N43 : A : 1003 5060(2010) 08 1253 04 Design of DDR2 SDRAM controller based on Verilog HDL ZHOU Liang, WANG Juan, HU Chang hua, YAN G Ming wu, GA O Ting ting ( School of Electr onic Science and Applied Physics, Hefei Univer sity of T echnology, Hefei 230009, China) Abstract :The key technologies of DDR2 SDRAM controller such as structure, interface and timing are explored in this paper. By top down method, several functional modules of controller are designed by Verilog HDL. T he design is simulated and verified by Modelsim 61 1 and synthesized by Synopsys De sign Compiler, and then implemented by Altera FPGA. T he simulation results show that the control ler is fully suitable for the DDR2 SDRAM control. Key words: DDR2 SDRAM; controller; V erilog HDL; field programmable gate array( FPGA) 0 1 DDR2 SDRA M , DDR2JEDEC DDR , , DDR DDR2 100 MHz , DDR2 400 MB/ s , 11 8 V , , , , DDR2 CASOCDODT , FPGA ASIC 2 , DDR , DDR2 DDR Verilog HDL , DDR2 SDRAM , , ,