VHDL语言UART串行接口芯片的设计程序清单.docVIP

VHDL语言的UART串行接口芯片设计程序清单附录1 数据接收据器的VHDL语言描述清单LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;use ieee.std_logic_signed.all; ENTITY UART_receiver ISPORT(RxD, Bclkx8, sysclk, reset, RDRF:IN STD_LOGIC;?????? RDR:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);?????? setRDRF, setOE, setFE:OUT STD_lOGIC);END UART_receiver; ARCHITECTURE rtl OF UART_receiver IS TYPE stateTYPE IS (R_WAiT, START_DETECTED,R_DATA);SIGNAL state, nextstate:stateTYPE;SIGNAL RSR:STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL cnt1:INTEGER RANGE 0 TO 7;SIGNAL cnt2:INTEGER RANGE 0 TO 8;signal clr1,clr2 : std_logic;SIGNAL inc1, inc2, shftRSR, loadRDR : STD_LOGIC;SIGNAL Bclkx8_Dlayed, Bclkx8_rising:STD_LOGIC; BEGINBclkX8_rising=Bclkx8 AND (NOT Bclkx8_dlayed);R_control:PROCESS(state,RxD,RDRF,cnt1,cnt2,BclkX8_rising)BEGIN--inc1=0;inc2=0;--clr1=0;clr2=0;shftRSR=0; loadRDR=0; setRDRF=0; setOE=0; setFE=0;CASE state IS??? WHEN R_WAIT =???????? IF(Rxd=0)THEN nextstate=START_DETECTED;??????????? ELSE nextstate=R_WAIT;???????? END IF;???? WHEN START_DETECTED=??????????? IF(Bclkx8_rising=0)THEN ?????????????? nextstate=START_DETECTED;??????????? ELSIF(RxD=1) THEN ?????????????? clr1=1;nextstate=R_WAIT;??????????? ELSIF(cnt1=3) THEN ?????????????? clr1 =1; nextstate=R_WAIT;??????????? ELSE ?????????????? inc1=1;nextstate=START_DETECTED; ??????????? END IF;WHEN R_DATA =??? IF(Bclkx8_rising=0) THEN nextstate=R_DATA;ELSE inc1=1;IF(cnt1 /= 7) THEN nextstate=R_DATA;ELSIF(cnt2/=8) THEN????? shftRSR=1; inc2=1; clr1=1;???? nextstate=R_DATA;ELSE???? Nextstate=R_WAIT;???? setRDRF=1; clr1=1; clr2=1;???? IF(RDRF=1) THEN setOE=1;???? ELSIF(RXD=0) THEN setFE=1;???? ELSE loadRDR=1;???? END IF;????????????????? END IF;??????????? END IF;???? END CASE;END PROCESS;R_update:PROCESS(sysclk,reset)BEGINIF(reset=0) THEN state=R_WAIT;BclkX8_Dlayed=0;???? cnt1=0; cnt2=0;ELSIF(syscLkEVENT AND sysclk=1) THEN??? state=nextstate;??? IF(clr1=1) THEN cnt