An Accelerator for Double Precision Floating Point Operations文献资料.pdfVIP

An Accelerator for Double Precision Floating Point Operations G. Danese, I. De Lotto, F. Leporati, M. Scaricabarozzi, A. Spelgatti Dip di Informatica e Sistemistica – Università di Pavia – via Ferrata, 1 INFM sez. Pavia – via Bassi, 6 – 27100 Pavia, Italia Tel. 39 0382 505350 – Fax 39 0382 505373 – e-mail: francesco.leporati@unipv.it Abstract computing power could ideally be the sum of the single We describe DPFPA (Double Precision Floating ones; [2] Point Accelerator) an FPGA based coprocessor • implementing dedicated hardware systems interfaced to the CPU through the PCI bus; it is (accelerators) able to speed up those operations which conceived to accelerate the evaluation of double represent the core of the calculations done. These precision floating point operations. This coprocessor is systems are then embedded in PC or workstations which based on two double precision floating point units: a drive their activity and manage the results [3]. pipelined adder and a pipelined multiplier. The work is Moreover a hybrid approach consisting in clusters of part of a global project aimed to design and build a accelerated workstations is becoming more and more parallel system made up by a cluster of accelerated diffused (see GIMPS, SETI, ASCI RED or ASCI White workstations. First estimations of performance have been