组合逻辑电路小世界网络模型.pdfVIP

10 4 V o l10 N o4 2006 7 ELE CT R IC M A CH INE S A N D CONT RO L Ju ly 2006 王哈力, 单 薏, 王希凤 ( , 150040) : 针对可编程逻辑器件中组合逻辑电路的优化设计问题, 依据复杂网络理论中小世 模型 分簇的基本特征, 提出了双重优化设计指标下的电路设计方法, 以 16 位奇偶校验电路为例, 利用 M a lab 对电路进行了仿真仿真结果表明, 通过适当降低网络分簇度, 有效削弱关键节点在电路中 的作用, 并适当增加网络连接的冗余性, 避免关键元器件的故障导致整 个系统的灾害性失败的现象 出现, 从而降低电路的脆弱性, 提高电路鲁棒性和可靠性 : 小世 网络模型; 平均分布度; 分簇系数; 平均路径长度 : TP393 : A : 1007- 449X ( 2006) 04- 0 370- 05 The sm allworld network m odel of combinational logic circuits W ANG H al,i SHAN Y ,i W AN G X ifeng ( Co llege o f E lec ica l E lec ron ic Eng ineering, H arbin U niversi y of Sc ience and T echno logy, H arb in 150040, Ch ina) Abs tract: F or op mi iza ion design o f com b ina orial log ic circui of programm ab le log ic dev ice, he design m e hod o f c ircui is presen ed based on doub leop mi iza ion index according o basic charac eris ic o f sm a llw orld m odel clu s ering o f com p lex ne work. U sing 16 b i pariy c ircu i as an exam ple w hich is smi u la ed u sing M a lab. Smi u la ion resu l s prove ha he m e hod w eakens func ion of key node in circu i effec ive ly by reducing ne w ork clus ering properly, and avo id he phenom enon ha fau l of key com ponen leads o ca as rophic fa ilure of he w ho le sys em by enhancing redundancy of ne w ork connec ions proper ly, hus, reduc frang ib iliy and mi prove robu s ness and reliab ili y of circu i. K ey w ord s: sm a llwo rld ne w ork m odel; average degree of dis ribu ion; clus ering coeffic ien ; average pa h leng h , ,