低频、低功耗CMOSLNA的设计优化技术.docVIP

低频、低功耗CMOS LNA的设计优化技术 胡小丽1,2，吴秀山1,3 （1.东南大学 信息科学与工程学院，江苏 南京 210096；2. 南京信息职业技术学校 电子信息工程系，江苏 南京 210046；3. 中国计量学院 机电工程学院， 浙江 杭州 310018） 【摘 要】分析了具有源级退化电感的CMOS共源共栅结构电路在低频、低功耗LNA设计中存在的缺陷，为满足低频、低功耗设计的要求现经常采用在该电路结构基础上再并联栅极电容的结构。本文按照噪声系数的定义严格推导了该结构电路的噪声参数表达式，并基于推导的公式分析了该结构在CMOS低频、低功耗LNA设计中的重要应用。最后实现了一个基于0.18μm CMOS工艺的ISM频段应用的433MHz LNA的设计，运用Agilent公司的设计仿真软件ADS进行仿真,整个LNA的设计过程和ADS仿真结果与理论分析一致。 【关键词】CMOS；共源共栅；LNA；低功耗；噪声系数；噪声优化 【中图分类号】TN924 【文献表示码】 A ________________________________________________________ Low frequency and low power CMOS LNA design optimization techniques HU Xiao-li1, 2 , WU Xiu-shan3 (1. Information science and Technology Institute, Southeast University, Nanjing 210096, China; 2. Department of Electronic Information Engineering , Najing College of information Technology, Nanjing 210046, China; 3.College of Electrical Mechanical Engineering, China Jiliang University, Hangzhou 310018，China） Abstract: This paper analyzes the fault of the cascode topology with the source degeneration inductance for CMOS low frequency and low power LNA design optimization techniques. To satisfy these requirements, now a cascode topology with the source degeneration inductance and with the gate parallel capacitance is usually to be used. In this paper we present a detailed and strict analysis the noise parameters of this architecture according to the definition of noise figure, based on these deduced equations, we furthermore discuss the important uses of this topology for CMOS low frequency and low power LNA design optimization techniques. In the last of this paper, we realize a 433MHz LNA used for ISM(Industrial-Scientific-Medical) based on the 0.18μm CMOS process, through the ADS of Agilent simulation, the overall design behavior and the implemented simulation results shows good agreement with theoretical analysis. Key words: CMOS；cascode；low-noise amplifier(LNA)；low power；noise figure；noise optimization 无线通信系统射频接收机的典型组成结构中，LNA是第一级有源电路，其噪声、非线性、匹配等性能对整个接收机至关重要，一