9. Code Scheduling for ILP-Processors.ppt

9. Code Scheduling for ILP-Processors {Software! compilers optimizing code for ILP-processors, including VLIW} 9.1 Introduction 9.2 Basic block scheduling 9.3 Loop scheduling 9.4 Global scheduling Typical layout of compiler:traditional, optimizing, pre-pass parallel, post-pass parallel Levels of static scheduling Contrasting the performance of {software/hardware} static code schedulers and ILP-processor 9.1 Basic Block Schedulers: List scheduler: in each step Basic Block: straight-line code, can only enter at beginning and left at end -Eligible Instructions are dependency-free no predecessors in the Data Dependency Graph or data to be produced by a predecessor node is already available timing: checking when the data will be ready hardware required resources are available -Looks for the ‘Best Choice’ from the eligible set of instructions {critical path in Data Dependency Graph} Choose First: Schedule instructions in the critical path Choose Next: others Heuristic Rule for choosing the next instructions Set of criteria 1. whether there is an immediate successor that is dependent on the instruction in question 2. how many successors the instruction has 3. how long is the longest path from the instruction in question to the leaves Case Study: compiler for IBM Power1 Basic block approach: list scheduler Using Data Dependency Graph Critical path the longest (in term of execution time) Earliest time when check the data for the instruction will be available Latency value (on each arc of DDG) how many time units the successors node have to wait before the result of the predecessor node becomes available Example program: The intermediate code and the corresponding DDG The first three steps in scheduling the example DDG using Warren‘s algoruthm Successive steps in scheduling the example DDG Successive steps in scheduling the example DDG 9.3 Loop Scheduling -Loop Unrolling for I = 1 to 3 do { b(I) = 2 * a(I) } Loop Unrolled: basic concept b(1) = 2 * a(1) b(2) = 2 * a