CMOS数字电路低功耗的层次化设计.pdf

100 25 1 , 200 8 1 CM OS 高 丹, 刘海涛 ( , 200050) : 随着芯片上可以集成越来越多的管子, 电路规模在不断扩大, 工作 率在不断提高, 这直接导致芯片功耗 的迅速增长, 无论是从电路可靠性来看, 还是从能量受限角度来讲, 低功耗都已成为CM O S 数字电路设计的重要内 容由于不同设计抽象层次对电路功耗的影响不同, 对各有侧重的低功耗设计方法和技术进行了讨论, 涉及到工 艺, 版图, 电路, 逻辑, 结构, 算法和系统等不同层次在实际设计中, 根据具体应用环境, 综合不同层次全面考虑功 耗问题, 可以明显降低电路功耗 : 低功耗; CM OS; 抽象层次 : T N 432 : A : 1000 - 7180( 2008) 0 1- 0 100- 04 Design of Low Power CMOS Digital Circuits at Abstraction Levels GAO Dan, L IU H a-i ao ( Shanghai Ins i u e of M icrosys em and Informa ion Technology , Chinese A cademy of Sciences, Shanghai 200050, China) Abstract: As he densi y, size and frequency of he chip co n inue o increase, pow er dissipa ion has emer ged as an impor- an design parame er in CM O S dig i al cir cui s, for he por able applica io ns and he sys em reliabili y . T his paper surveys design echniques arge ing low pow er dissipa ion in CM OS digi al cir cui s a various levels of abs rac ion , including pro- cess, layou , circui , logic, archi ec ural, alg ori hmic and sys em . Ac ually pow er dissipa ion can be reduced obviou sly w i h some diff er en echniques oge her . Key words: lo w pow er ; CM OS; abs rac ion levels , PM OS ( 1 ) , N MOS ( ) , N P , , ( ) , 1( a) , i r ev ( 1) , , A D , , J S , , I L = A D J S ( 1) , 2. 1. 2 亚阈值电流功耗 VGS V h , M OS 2 CM OS , , , 1( a) i sub CMOS , , , , , , , 2. 1. 3 直流偏置电流功耗 C