The M2 ASIC.ppt

SAAB SPACE The M2 ASIC A mixed analogue/digital ASIC for acquisition and control in data handling systems M2 summary A mixed analogue/digital ASIC, including 32 kgates and a 12 bit ADC, developed by Austrian Aerospace and Saab Space under an ESA contract Main application as generic core circuit for data handling I/O board Controlled via OBDH bus or UART interface Digital I/O functions include all common data handling system interfaces, such as: High level command pulse generation Serial command and acquisition Etc. 3.3V supply Low power, typical consumption 12mW M2 block diagram M2 implementation Commercial, epi-layered CMOS technology, AMIS 0.35μ with analog options (double poly capacitors, high resistive poly resistors) Radiation tolerant by “Rad hard by design” Digital cell library developed within the project Digital part designed using VHDL, logic synthesis and place route Chip size 25mm2 Prototypes via Europractice MPW in 160 pin CQFP package Tested showing full functionality and full performance at first run Implemented on a prototype I/O board for system level test, showing similar or better performance compared to existing designs Rad hard by design The methodology to reach radiation hardness has basically been the same for analogue and digital parts. This includes: Selection of submicron CMOS assures small threshold voltage drifts NMOS edge leakage avoided by enclosed shaped transistors Leakage between NMOS devices avoided by guard rings Latchup avoided by guard rings and good substrate connections SEU hardness achieved by means of resistive feedback in flip-flops Limits maximum possible clock rate, but Makes the design hard also to transients in combinatorial logic Only low level measures, mainly on layout level, to achieve radiation hardness ? radiation aspects have only marginal impact on system, VHDL and schematic level design Cell library design based on “shadow” library Cell library, just like analog parts and top level design, developed using a l