Lecture 14 VHDL Modeling of Sequential Machines.ppt

ECE C03 Lecture 14 Lecture 14 VHDL Modeling of Sequential Machines Hai Zhou ECE 303 Advanced Digital Design Spring 2002 Outline Describing Sequential Behavior in VHDL Latches Flip-Flops Finite State Machines Synthesis Using VHDL Using Packages in VHDL READING: Dewey 17.1, 17.3, 17.4, 17.5, 17.6, 17.7, 17.8, 17.10, 18.1, 18.2 Latches Latches are easily described by using the concurrent signal assignment statement entity JK_LATCH is port ( J, K : in BIT; Q : inout BIT := ‘0’; Q_BAR : inout BIT := ‘1’;) end JK_LATCH; architecture TRUTH_TABLE of JK_LATCH is begin -- Map truth table into conditional concurrent statements Q = Q when (J = ‘0’ and K = ‘0’) else ‘0’ when (J = ‘0’ and ‘K=‘1’) else ‘1’ when (J=‘1’ and K = ‘0’) else Q_BAR; Q_BAR = not Q; end TRUTH_TABLE; Level-sensitive Synchronous Behavior When a control signal like a clock controls whether the gated latch responds to inputs entity JK_GATED_LATCH is port ( J, K, CLK : in BIT; Q : inout BIT := ‘0’; Q_BAR : inout BIT := ‘1’;) end JK_LATCH; architecture TRUTH_TABLE of JK_GATED_LATCH is begin CLKED : block (CLK = ‘1’) -- guard expression begin Q = guarded Q when (J = ‘0’ and K = ‘0’) else ‘0’ when (J = ‘0’ and ‘K=‘1’) else ‘1’ when (J=‘1’ and K = ‘0’) else Q_BAR; Q_BAR = not Q; end block CLKED; end TRUTH_TABLE; Block Statements A block statement provides a way to combine a group of concurrent statements together A group of statements can be placed under a guard FORMAT label: block (guard expression) -- declarative part begin -- statement part end block label A guard is a boolean expression that evaluates to true or false. Concurrent statements in block execute if guard is true Guarded Statement A guarded assignment statement executes if either (1) the guard expression changes from FALSE to TRUE (2) The guard expression is TRUE and one of the signals appearing on the right hand side of the signal assignment changes value Example: B1 : block (CONTROL_SIGNAL = ‘1’) begin X = gu