4 bit Versatile CMOS Rate Multiplier.ppt

4 bit Versatile CMOS Rate Multiplier Hardik Parikh Akshay Bhat Alex Jose Swastick Biswas Advisor: Dave Parent DATE: 05/11/2005 Agenda Abstract Introduction What is a Rate Multiplier and applications Cumulative adder Principle Improvements made to make the circuit versatile Project Highlight Project Details Results Cost Analysis Conclusion Abstract We designed a 4-bit rate multiplier that operates at 200 MHz and uses 18.9mW of Power and occupies an area of 380 x 200 mm2 Introduction Rate Multiplier: A digital circuit that multiplies the incoming clock by a ratio to give an output pulse rate: where, P and Q are integers and P Q This is not a frequency divider as numerator P is not one Application: * Arithmetic Mathematic Functional generation * PCM systems * Motor Control Systems * Vector Generation Interpolation * Frequency Synthesizer Introduction Introduction Project highlight Programmable rates that broaden the application area considerably High speed implementation through Carry look ahead adders Optimally spaced output pulse distribution Cascadable in multipliers of 4 bits Most of the standard industry chips are BCD rate multipliers. This rate multiplier is more versatile as the denominator Q is programmable. Architecture Style Architecture Style Architecture Style Longest Path Calculation Longest Path Calculations Schematic Floor Plan Layout Verification Simulation 1 Simulation 2 Power Analysis Cost Analysis Time spent on each phase of the project in man hours Verifying logic: 10 Schematic, sizing and verifying timing: 40 Layout: 140 Post extracted timing: 5 Lessons Learned Have a rough idea of DRC rules before sizing the transistors. We underestimated the DRC minimum metal spacing only to find that the design became too tight. Before starting layout spend time on making a floor plan Document your design Using Cell based design makes life easy! It reduces debug time Time management