NetFPGA Project4-Port Layer 23 Switch.ppt

NetFPGA Project:4-Port Layer 2/3 Switch Ankur Singla (asingla@stanford.edu) Gene Juknevicius (genej@stanford.edu) Agenda NetFPGA Development Board Project Introduction Design Analysis Bandwidth Analysis Top Level Architecture Data Path Design Overview Control Path Design Overview Verification and Synthesis Update Conclusion NetFPGA Development Board Project Introduction 4 Port Layer-2/3 Output Queued Switch Design Ethernet (Layer-2), IPv4, ICMP, and ARP Programmable Routing Tables – Longest Prefix Match, Exact Match Register support for Switch Fwd On/Off, Statistics, Queue Status, etc. Layer-2 Broadcast, and limited Layer-3 Multicast support Limited support for Access Control Highly Modular Design for future expandability Bandwidth Analysis Data Flow Diagram Output Queued Shared Memory Switch Round Robin Scheduling Packet Processing Engine provides L2/L3 functionality Coarse Pipelined Arch. at the Block Level Master Arbiter Round Robin Scheduling of service to Each Input and Output Interfaces Rest of the Design with Control FPGA Co-ordinates activities of all high level blocks Maintains Queue Status for each Output Ingress FIFO Control Block Interfaces three blocks Control FPGA Forwarding Engine Packet Buffer Controller Dual Packet Memories for coarse pipelining Responsible for Packet Replication for Broadcast Packet Processing Engine Overview Goals Features – L3/L2/ICMP/ARP Processing Performance Requirements – 78Kpps Fit within 60% of Single User FPGA Block Modularity / Scalability Verification / Design Ease Actual Support for all required features + L2 broadcast, L3 multicast, LPM, Statistics and Policing (coarse access control) Performance Achieved – 234Kpps (worst case 69Kpps for ICMP echo requests 1500bytes) Requires only 12% of Single UFPGA resources Highly Modular Design for design/verification/scalability ease Pkt Processing Engine Block Diagram Forwarding Master State Machine Responsible for controlling individual processing blocks Reques