Introduction toCMOS VLSIDesignDesign for Low Power.ppt

18: Design for Low Power Introduction toCMOS VLSIDesignDesign for Low Power Outline Power and Energy Dynamic Power Static Power Low Power Design Power and Energy Power is drawn from a voltage source attached to the VDD pin(s) of a chip. Instantaneous Power: Energy: Average Power: Dynamic Power Dynamic power is required to charge and discharge load capacitances when transistors switch. One cycle involves a rising and falling output. On rising output, charge Q = CVDD is required On falling output, charge is dumped to GND This repeats Tfsw times over an interval of T Dynamic Power Cont. Dynamic Power Cont. Activity Factor Suppose the system clock frequency = f Let fsw = af, where a = activity factor If the signal is a clock, a = 1 If the signal switches once per cycle, a = ? Dynamic gates: Switch either 0 or 2 times per cycle, a = ? Static gates: Depends on design, but typically a = 0.1 Dynamic power: Short Circuit Current When transistors switch, both nMOS and pMOS networks may be momentarily ON at once Leads to a blip of “short circuit” current. 10% of dynamic power if rise/fall times are comparable for input and output Example 200 Mtransistor chip 20M logic transistors Average width: 12 l 180M memory transistors Average width: 4 l 1.2 V 100 nm process Cg = 2 fF/mm Dynamic Example Static CMOS logic gates: activity factor = 0.1 Memory arrays: activity factor = 0.05 (many banks!) Estimate dynamic power consumption per MHz. Neglect wire capacitance and short-circuit current. Dynamic Example Static CMOS logic gates: activity factor = 0.1 Memory arrays: activity factor = 0.05 (many banks!) Estimate dynamic power consumption per MHz. Neglect wire capacitance. Static Power Static power is consumed even when chip is quiescent. Ratioed circuits burn power in fight between ON transistors Leakage draws power from nominally OFF devices Ratio Example The chip contains a 32 word x 48 bit ROM Uses pseudo-nMOS decoder and bitline pullups On average, one wordlin