[ECE VHDL 课件] ECE 448 FPGA and ASIC Design with VHDL - 10 memories.ppt

Memory Types CLB Slice Distributed RAM CLB LUT configurable as Distributed RAM A LUT equals 16x1 RAM Implements Single and Dual-Ports Cascade LUTs to increase RAM size Synchronous write Synchronous/Asynchronous read Accompanying flip-flops used for synchronous read FPGABlock RAM(BRAM) Block RAMs in Xilinx Spartan 3 FPGAs Most efficient memory implementation Dedicated blocks of memory Ideal for most memory requirements 4 to 104 memory blocks 18 kbits = 18,432 bits per block (16 k without parity bits) Use multiple blocks for larger memories Can be used to build both single-port and true dual