[ECE VHDL 课件] ECE 448 FPGA and ASIC Design with VHDL - 2 VHDL_refresher.pptVIP

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[ECE VHDL 课件] ECE 448 FPGA and ASIC Design with VHDL - 2 VHDL_refresher.ppt

VHDL Refresher Required reading Recommended reading Recommended reading Recommended reading for next week VHDL VHDL is a language for describing digital hardware used by industry worldwide VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language Genesis of VHDL Multiple design entry methods and hardware description languages in use No or limited portability of designs between CAD tools from different vendors Objective: shortening the time from a design concept to implementation from 18 months to 6 months A Brief History of VHDL June 1981: Woods

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