[ECE VHDL 课件] ECE 448 FPGA and ASIC Design with VHDL - 1 introduction.pptVIP

ECE 448 FPGA and ASIC Design with VHDL Spring 2007 Levels of design description Register Transfer Level (RTL) Design Description VHDL Design Styles Testbenches Testbench Environment World of Integrated Circuits FPGA Design process (1) FPGA Design process (2) Simulation Tools FPGA Synthesis Tools FPGA Implementation After synthesis the entire implementation process is performed by FPGA vendor tools Top Level ASIC Digital Design Flow ASIC Simulation Tools ASIC Synthesis Tools XESS Inc. Educational Boards Celoxica RC10 Educational Board Design Process control from Active-HDL RTL Design Place