[ECE VHDL 课件] ECE 448 FPGA and ASIC Design with VHDL - 16 ASIC front end design.pptVIP

ASIC Front-End Design Source: I. Kuon, J. Rose, University of Toronto “Measuring the Gap Between FPGAs and ASICs” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 62, no. 2, Feb 2007. Simplified ASIC Design Flow Major ASIC Toolsets Simplified ASIC Design Flow A Complete Placed and Routed Chip What is “Physical Layout”? Process of Device Fabrication Devices are fabricated vertically on a silicon substrate wafer by layering different materials in specific locations and shapes on top of each other Each of many process masks defines the shapes and locations of