[ECE VHDL 课件] ECE 448 FPGA and ASIC Design with VHDL - 12 HLL design methodology.ppt

High Level Language (HLL)Design MethodologyHandel C Main sources Behavioral Synthesis Need for High-Level Design Higher level of abstraction Modeling complex designs Reduce design efforts Fast turnaround time Technology independence Ease of HW/SW partitioning Advantages of Behavioral Synthesis Easy to model higher level of complexities Smaller in size source compared to RTL code Generates RTL much faster than manual method Multi-cycle functionality Loops Memory Access High-Level Languages C/C++-Based Handel C – Celoxica Ltd., UK Impulse C – Impulse Accelerated Technologies Catapult C –