加法器、减法器的设计 VHDL.docVIP

实 验 报 告 课程名称 电子设计自动化实验（基于FPGA）LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE IEEE.std_logic_arith.all; USE IEEE.std_logic_unsigned.all; ENTITY add IS PORT(a:in std_logic_vector(7 downto 0); b:in std_logic_vector(7 downto 0); ctrl:in std_logic; bcd:out std_logic_vector(15 downto 0)); END ENTITY; ARCHITECTURE func OF add IS SIGNAL x:std_logic_vector(9 downto 0); SIGNAL y:std_logic_vector(9 downto 0); SIGNAL z:std_logic_vector(9 downto 0); SIGNAL c:std_logic_vector(8 downto 0); SIGNAL dec:integer; BEGIN yunsuan:BLOCK --运算模块 BEGIN PROCESS(a) BEGIN IF (a(7) = 0)