Quartus常见错误分析.pdfVIP

1 Warning: VHDL Process Statement warning at random.vhd(18): signal reset is in statement, but is not in sensitivity list 没把singal 放到process （）中 2 Warning: Found pins ing as undefined clocks and/or memory enables Info: Assuming node CLK is an undefined clock -=可能是说设计中产生的触发器没有使能端 3 Error: VHDL Interface Declaration error in clk_gen.vhd(29): interface object clk_scan of mode out cannot be read. Change object mode to buffer or inout. 信号类型设置不对，out 当作buffer 来定义 4 Error: Node instance clk_gen1 instantiates undefined entity clk_gen 引用的例化元件未定义实体－－entity clk_gen 5 Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew Info: Detected ripple clock clk_gen:clk_gen1|clk_incr as buffer Info: Detected ripple clock clk_gen:clk_gen1|clk_scan as buffer 6 Warning: VHDL Process Statement warning at ledmux.vhd(15): signal or variable dataout may not be assigned a new in every possible path through the Process Statement. Signal or variable dataout holds its previous in every path with no new assignment, which may create a combinational loop in the current design. 7 Warning: VHDL Process Statement warning at divider_10.vhd(17): signal cnt is read inside the Process Statement but isnt in the Process Statements sensivitity list 缺少敏感信号 8 Warning: No clock transition on counter_bcd7:counter_counter_clk|q_sig[3] register 9 Warning: Reduced register counter_bcd7:counter_counter_clk|q_sig[3] with stuck clock port to stuck GND 10 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock class[1] with clock skew larger than data delay. See Compilation Report for details. 11 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock sign with clock skew larger than data delay. See Compilation Report for details. 12 Error: VHDL error at counter_clk.vhd(90): actual port class of mode in cannot be associated with