一种用于数字集成系统的新型CMOS三态缓冲器的设计.pdf

第30 卷 第6 期 电 子 器 件 Vol. 30 N o. 6 2007 年12 月 Chine se Jour n al Of Elect r on Dev ic es Dec. 2007 Design of A Novel CMOS Three2State Buffer for Digital Integrated Systems 1,2 1, * PENGKe , YANG H ai2gang 1. The State Key Lab of Transducer Technology, Institute of Electronics, AS, Beijing 100080, hina; 2. Graduate University of the hinese Academy of Sciences, Beijing 100039, hina Abstract:Th e t hree2st at e logic is widely u sed in VL SI digit al sy st ems Th ere are many ways for realizat ion of t h e CM OS t hree2st ate circu it But t h ey eith er t ake t oo mu ch area or lack of t h e drive st ren gt h A n ovel CM OS t hr ee2st at e buffer is prop osed based on t he research int o t radit ional three2st at e bu ffer s To t he b est of our knowledge, t his is a three2st at e bu ffer wit h minimum numb er of t ran sist or s SPICE simu lat ion dem2 onst rat es t hat t h e proposed t hr ee2st at e buffer present s opt imum area2delay product ch aract er ist ic and lower st atic p ower dis sip at ion comp ared wit h ot h er t radit ion al on es Key ords:VLSI ; CM OS; Three2Stat e; Area2Delay Produ ct EEACC:1265; 2570D CMOS 1, 2 1, * 彭 科 , 杨海钢 1 , 100080; 2 , 100039 : V LSI , , , SPICE , - : V L SI; CMO S; ; - :TN431. 1 :A :100529490(2007)0622080204 , , , SPICE , VL SI , , , - , Mentor Graphics [ 1] , SMIC 0 18 Lm , : 1 4 , [ 223, 6]