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在AlteraPFGA上实现POWERLINK从站设计
User Guide
openPowerlink FPGA Slave
Reference Design
Author: Zelenka Joerg
Version: V1.0
Date: 27/10/2009
File: User Guide.doc
User Guide: OpenPowerlink FPGA Slave Reference Design
INDEX
1 Document Overview 3
2 Design Features 3
3 Performance Restriction 3
4 Requirements 3
5 Quick Start 4
5.1 Unzip Package 4
5.2 Build Makefile 5
5.3 Program FPGA (Hardware) 6
5.4 Program Nios II CPU (Software) 7
5.5 Run a Nios II Terminal (immediate debugging) 8
6 Quartus II 8
7 Nios II IDE 9
7.1 Import Software Projects 9
7.2 Configure Target Connection12
7.3 Run or Debug Target 12
8 Troubleshooting13
27/10/2009 Zelenka Joerg
User Guide.doc
User Guide: OpenPowerlink FPGA Slave Reference Design
1 Document Overview
This document gives you a “Quick Start” instruction (5 @ page 4) to su essfully run the
openPowerlink FPGA Slave Reference Design in a few minutes. In addition the
performance restrictions (3 @ page 3) are given and should be considered at any time!
In chapter 6 the steps are given to import the software projects into Nios II IDE to start
development. In case of error messages please refer to section 8 starting at page 13.
2 Design Features
The openPowerlink FPGA Slave Reference Design uses one TXPDO and two RXPDOs (refer
to Table 21).
Table 2-1: PDOs
Source/Sink on EvalBoard I/O Size PDO Index
4 Buttons Input 8 Bits (lower n
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