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A HardwareSoftware Partitioning and Scheduling Algorithm for Dynamically Reconfigurable Em.pdf

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A HardwareSoftware Partitioning and Scheduling Algorithm for Dynamically Reconfigurable Em

A Hardware-Software Partitioning and Scheduling Algorithm for Dynamically Reconﬁgurable Embedded Systems Bingfeng Mei Patrick Schaumont Serge Vernalde IMEC vzw, Kalpedreef 75, B-3001, Leuven, Belgium Department of Electrical Engineering, K. U. Leuven, B-3001, Leuven, Belgium Phone:+32(0)16 281 835 Fax:+32(0)16 281 515 E-mail: bennet, schaum, vernalde@imec.be Abstract— Dynamically reconﬁgurable embedded systems ogy from a system point of view. (DRESs) target an architecture consisting of general- Hardware-software co-design research deals with how purpose processors and ﬁeld programmable gate arrays (FPGAs), in which FPGAs can be reconﬁgured in run-time to design heterogeneous systems. The main goal is to achieve cost saving. to shorten the time-to-market while reducing the de- In this paper, we describe a hardware-software partition- sign effort and costs of designed products. The normal ing and scheduling approach for DRESs. Previous work design ﬂow includes system speciﬁcation, cost estima- only took conﬁguration time into account, without consid- ering partial reconﬁguration. With partial reconﬁguration, tion, hardware-software partitioning, co-synthesis and co- the scheduling on FPGAs becomes a constrained placement simulation. Since DRESs consist of both processor and problem, whereas scheduling on application-speciﬁc inte- FPGAs, they ﬁt into a co-design ﬂow naturally. However, grated circuits (ASICs) is a serialization problem. Here we due to reconﬁgurablity of FPGAs, there are some signiﬁ- present