DRAFT A Scanning Test Methodology for Dynamic and Partially Reconfigurable FPGAs.pdfVIP

DRAFT: A Scanning Test Methodology for Dynamic and Partially Reconfigurable FPGAs Manuel G. Gericota, Gustavo R. Alves Miguel L. Silva, José M. Ferreira ISEP – Rua Dr. António Bernardino de Almeida FEUP – Rua Dr. Roberto Frias 4200-072 Porto - PORTUGAL 4200-465 Porto - PORTUGAL Abstract proposed to test the FPGA Configurable Logic Blocks (CLBs). A new class of FPGAs that enable partial and dynamic reconfiguration without disturbing system operation, In our approach, configuration memory is considered fault free and will not be tested. Nevertheless, the same test raised a new test challenge: how to assure a continuously fault free operation, independently of the circuit present infrastructure could be used to perform a readback of the after many reconfiguration processes. configuration data loaded into the FPGA, helping to detect faults in the configuration elements. A new on-line test method for those FPGAs is proposed, based on a scanning methodology and in the reuse of the We start by a general description of the structural IEEE 1149.1 Boundary Scan test infrastructure, already concurrent test solution envisaged for the CLBs of an widely employed for In-System Programming. FPGA,