Efficient Generation of PreSilicon MOS Model Parameters for Early Circuit Design.pdfVIP

156 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 1, JANUARY 2001 Efficient Generation of Pre-Silicon MOS Model Parameters for Early Circuit Design Michael Orshansky, Judy An, Chun Jiang, Bill Liu, Concetta Riccobene, and Chenming Hu Abstract— The technology development cycle continues to Prediction of source/drain parasitic resistance is also crucial for shrink, which very often requires evaluation of circuit design accurate prediction of device performance characteristics. and technology choices using circuit simulators at the time Second, in order to guarantee that the resulting SPICE model when no real silicon is available. In this paper, we present an efficient methodology for generating pre-silicon device models file (a set of model parameters) is a close representation of a for advanced CMOS processes. The methodology allows accurate real future device, some critical parameters need to be explic- prediction of the full MOS – characteristics for the future itly targeted. For example, the linear region threshold voltage technologies combining a constraint back-propagation algorithm , and the saturation voltage of a nominal device are based upon a few critical specifications, physical models for the critical. BSIM3v3 has no way of predicting the degree of short- advanced device phenomena, and the empirical data from devices of an existing technology. The methodology has been tested on channel effects (such as threshold voltage roll-off and drain-in- two CMOS production technologies. Good prediction results are duced barrier lowering) that are determined by a two-dimen- achiev