Guidelines for Safe Simulation and Synthesis of Implicit Style Verilog.pdfVIP

Guidelines for Safe Simulation and Synthesis of Implicit Style Verilog Mark G. Arnold Neal J. Sample James D. Shuler Computer Science Department Computer Science Department Computer Science Department University of Wyoming University of Wyoming SUNY Col lege at Brockport Laramie, Wyoming 82071 Laramie, Wyoming 82071 Brockport, New York 14420 marnold@uwyo.edu nsample@uwyo.edu jshuler@cs.br ockport.edu Abstract design with the implicit style is very similar to soft- We discuss the classes of machines for which im- ware design. The main distinction b etween software plicit style design is appropriate, and give guidelines and implicit style hardware is the issue of scheduling for safe simulation and synthesis of implicit style V er- computation relative to the clo ck. In contrast, hard- ilog that ensure the results of cycle based simulation ware design with the explicit style is far more tedious agree with the results of synthesis. We also propose a than typical software design. minor revision to IEEE 1364 for bottom testing loops The purp ose of this pap er is to describ e the \safe that improves the clarity of safe implicit style Verilog. subset of implicit style design that works for b oth sim- ulation and synthesis, and how such Verilog should b e 1 Intro duction co ded so that it can b e easily p orted b etween to ols. It Hardware systems of any complexity inevitably is the author