EDA实验报告硬件电子琴电路设计.docVIP

EDA实验报告 课程名称： EDA技术 实验名称： 硬件电子琴电路设计 班级： 姓名： 指导老师： 签名： 实验目的 学习利用数控分频器设计硬件电子琴实验。 实验仪器 计算机一台；Quartus Ⅱ软件；U盘。 实验内容与步骤 在Quartus Ⅱ完成音阶发生器模块TONE和数控分频器模块Speaker的设计，然后完成硬件电子琴顶层文件的设计，最后检查设计是否正确。 1、）VHDL程序）模块图形符号及逻辑功能描述 图2 数控分频器Speaker硬件电路 2、（VHDL程序LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY Tone IS PORT ( Index : IN STD_LOGIC_VECTOR(7 DOWNTO 0); CODE : OUT INTEGER RANGE 0 TO 15; HIGH : OUT STD_LOGIC; Tone : OUT INTEGER RANGE 0 TO 16#7FF# ); END; ARCHITECTURE one OF Tone IS BEGIN Search : PROCESS(Index) BEGIN CASE Index IS -- 译码电路，查表方式，控制音调的预置数 WHEN = Tone = 773; CODE = 1; HIGH = 0; WHEN = Tone = 912; CODE = 2; HIGH = 0; WHEN = Tone = 1036; CODE = 3; HIGH = 0; WHEN = Tone = 1116; CODE = 4; HIGH = 0; WHEN = Tone = 1197; CODE = 5; HIGH = 0; WHEN = Tone = 1290; CODE = 6; HIGH = 0; WHEN = Tone = 1372; CODE = 7; HIGH = 0; WHEN = Tone = 1410; CODE = 1; HIGH = 1; WHEN OTHERS = Tone = 2047; CODE = 0; HIGH = 0; END CASE; END PROCESS; END; （2）模块图形符号及逻辑功能描述3.顶层文件的设计 将音阶发生器模块TONE和数控分频器模块Speaker打包之后，接下来进行顶层文件的设计。 （1）完整的VHDL程序描述 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY TOP IS -- 顶层设计 PORT ( CLK12MHZ : IN STD_LOGIC; INDEX1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); CODE1 : OUT INTEGER RANGE 0 TO 15; HIGH1,SPKOUT : OUT STD_LOGIC ); END; ARCHITECTURE one_OF_TOP IS COMPONENT Tone PORT ( Index : IN STD_LOGIC_VECTOR(7 DOWNTO 0); CODE : OUT INTEGER RANGE 0 TO 15; HIGH : OUT STD_LOGIC; Tone : OUT INTEGER RANGE 0 TO 16#7FF# );