新现代计算机组成原理 教学课件 潘松 潘明 编著 第 6 章.pptVIP

现代计算机组成原理 潘 明 潘 松 编著 第 6 章 16位CISC CPU设计 when bgtI7 = outregRd = 1; next_state = bgtI8; when bgtI8 =outregRd = 1; progcntrWr = 1; addrregWr = 1; next_state = bgtI9; when bgtI9 = vma = 1; rw = 0; next_state = bgtI10; when bgtI10 = vma = 1; rw = 0; if ready = 1 then progcntrWr = 1; next_state = loadPc; else next_state = bgtI10; end if; when inc2 = regSel = instrReg(2 downto 0); regRd = 1; alusel = inc; shiftsel = shftpass; outregWr = 1; next_state = inc3; when inc3 = outregRd = 1; next_state = inc4; when inc4 = outregRd = 1; regsel = instrReg(2 downto 0); regWr = 1; next_state = incPc; when loadPc = progcntrRd = 1; next_state = loadPc2; when loadPc2 = progcntrRd = 1; addrRegWr = 1; next_state = loadPc3; when loadPc3 = vma = 1; rw = 0; next_state = loadPc4; when loadPc4 = vma = 1; rw = 0; if ready = 1 then instrWr = 1; next_state = execute; else next_state = loadPc4; end if; when incPc = progcntrRd=1; alusel=inc; shiftsel=shftpass; next_state=incPc2; when incPc2 = progcntrRd = 1; alusel = inc; shiftsel = shftpass; outregWr = 1; next_state = incPc3; when incPc3 = outregRd = 1; next_state = incPc4; when incPc4 = outregRd=1; progcntrWr=1; （接下页） addrregWr=1; next_state=incPc5; when incPc5 = vma = 1; rw = 0; next_state = incPc6; when incPc6 = vma = 1; rw = 0; if ready = 1 then instrWr = 1; next_state = execute; else next_state = incPc6; end if; when others = next_state = incPc; end case; end process; controlffProc:process(clock, reset) begin if reset = 1 then current_state = reset1 after 1 ns; elsif clockevent and clock = 1 then current_state = next_state after 1 ns; end if; end process; end rtl; 6.2 CPU基本部件设计 6.2.4 寄存器与寄存器阵列 图6-10 寄存器REG的实体结构和RTL图 1．寄存器REG 6.2 CPU基本部件设计 6.2.4 寄存器与寄存器阵列 1．寄存器REG 【例6-6】reg.vhd library IEEE; use IEEE.std_logic_1164.all; use work.cpu_lib.all; entity reg is port( a : in bit16; clk : in std_logic; q : out bit16); end reg; architecture rtl of reg is begin regproc: process begin wait until clk event and clk = 1; q =