CD4518 CMOS 双BCD加法计数器.pdfVIP

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4518B MSI Dual BCD counter Product specification January 1995 File under Integrated Circuits, IC04 Philips Semiconductors Product specification HEF4518B Dual BCD counter MSI DESCRIPTION LOW transition of the CP1 input if CP0 is LOW. Either CP0 or CP1 may be used as the clock input to the counter and T he HEF4518B is a dual 4-bit internally synchronous BCD the other clock input may be used as a clock enable input. counter. The counter has an active HIGH clock input A HIGH on MR resets the counter (O0 to O3 = LOW) (CP ) and an active LOW clock input (CP ), buffered 0 1 independent of CP , CP . 0 1 outputs from all four bit positions (O to O ) and an active 0 3 Schmitt-trigger action in the clock input makes the circuit HIGH overriding asynchronous master reset input (MR). highly tolerant to slower clock rise and fall