RevisedCourseStructureandSyllabus-B.Tech-Jawaharlal.docVIP

2010-11 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY KAKINADA Kakinada 533 003 II B.TECH. – I SEMESTER (COMMON FOR COMPUTER SCIENCE ENGINEERING AND INFORMATION TECHNOLOGY) REVISED COURSE STRUCTURE AND SYLLABUS – 2010-11 BATCH II Year – I Semester I SEMESTER P C S.No. Subject P C 1 Managerial Economics and Financial Analysis 4+1* 4 2 Probability Statistics 4+1* 4 3 Mathematical Foundations of Computer Science and Engineering 4+1* 4 4 Digital Logic Design 4+1* 4 5 Electronic Devices and Circuits 4+1* 4 6 Data Structures 4+1* 4 7 Electronic Devices and Circuits Lab 3 2 8 Data Structures Lab 3 2 9 Professional Communicational skills 2 1 Total Credits 29 *Tutorial 2010-11 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY KAKINADA B.TECH. (COMPUTER SCIENCE AND ENGINEERING) II Year B.Tech. – I Sem. DIGITAL LOGIC DESIGN Unit I : Number Systems Binary, Octal, Decimal, Hexadecimal Number Systems. Conversion of Numbers From One Radix To Another Radix , r’s Complement and (r-1)’s Complement Subtraction of Unsigned Numbers, Problems, Signed Binary Numbers, Weighted and Non weighted codes Unit II:Logic Gates And Boolean Algebra Basic Gates NOT, AND, OR, Boolean Theorms,Complement And Dual of Logical Expressions, Universal Gates, Ex-Or and Ex-Nor Gates, SOP,POS, Minimizations of Logic Functions Using Boolean Theorems, Two level Realization of Logic Functions Using Universal Gates. Verilog programming for the minimized logic functions. Unit III: Gate- Level Minimization Karnaugh Map Method(K-Map): Minimization of Boolean Functions maximum upto Four Variables , POS And SOP, Simplifications With Don’t Care Conditions Using K-Map. Unit IV: Combinational Arithmetic Logic Circuits Design of Half Adder, Full Adder, Half Subtractor , Full Subtractor, Ripple Adders and Subtractors, Ripple Adder/Subtractor Using Ones and Twos Complement Method. Serial Adder , Carry Look Ahead Adder. Unit V: Co