SDR中通用可编程零次群复分接芯片和其板级验证系统设计.pdfVIP

Abstract Abstract Based on the project of key Laboratory Fund of the Information and Communication Technology, this paper mainly studied the design and implementation of general programmable chip of zero group channel Muldex and its board-level verification system in software-defined radio SDR The system which has the natures of multi-service, multi-mode, reconfigurable, save resources and intelligence meets the requirement of SDR in practical application. For the continuous development and improvement of SDR, it is widely used in military, civil and aerospace applications. To open a separate channel for data transmission of the zero group slower than primary will waste a lot of system resources, which is not conducive to integration of equipment of the SDR system. At present, the zero group equipment is very few, and intelligence is very poor. According to the requirements of the system, the paper firstly identified the design of the digital muldex system, and proved the feasibility of the program by a lot of experiment and simulation. Then the design,synthesis,simulation are carried out by Quartus II, and layout for part of the system. Finally, the design of board-level verification platform is completed by Altium Designer, assembly, download, debugging and testing of the platform are also completed. It is verified that the chip design has a good feasibility and board-level verification platform has a good reliability. The paper presents the work done and innovations as follows: 1 Studying the digital, analog PLL and other methods, combined with equivalent, proposed a new fast clock recovery program, achieved zero group adaptive system. 2 Achieved the FPGA off-line reconstruction program of MCU+U disk, Loaded mass configuration data softly; and compared with other offline reconstruction schemes. 3 Achieved forward error correction