fpga power reduction using configurable dual-vdd.pptVIP

Scalable Symbolic Model Order Reduction Yiyu Shi*, Lei He* and C. J. Richard Shi+ *Electrical Engineering Department, UCLA +Electrical Engineering Department, University of Washington, Seattle This work is supported in part by NSF CAREER Award CCR-0306682, Defense Advanced Projects Agency under contract W31P4-05-O-R164 and in part by Defense Threat Reduction Agency under contract #FA9451-06-C-0384. Motivation With the advance of design technology, especially when we have entered the nano regime. Plenty of algorithms exist in literature discussing how to analyze and simulate those symbolic circuits. All those methods are practical only if the circuit has a moderate size. However, the circuits from physical extraction usually contain millions of nodes. Numerous model order reduction (MOR) techniques have been successfully applied to the reduction of linear large scale circuits over the past decade. However, despite their wide application, unsolved problems do exist when directly extending them to symbolic circuits. Symbolic model order reduction is proposed accordingly [Shi:tcad’06] Prior Art The idea of symbolic model order reduction (SMOR) was first introduced in [Shi:tcad’06], which contains three different methods Symbolic isolation It first removes all the symbols from the circuits, and the nodes to which the symbols are connected are modeled as ports. The time and space complexity for the reduced model increases cubically with the number of ports, i.e., the number of symbols Nominal projection It uses the nominal values of the symbols to compute the projection matrix. It is accurate only when the symbol values slightly deviate from the nominal value. First order expansion It uses the first order expansion of the matrix inversion and multiplication to find the projection matrix, which is first order matrix polynomial w.r.t. all the symbols. Again, no large change is allowed for the symbols in order for the method to be accurate. Major Contributio